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femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator ics843031-01 idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 1 ics843031ag-01 rev. a august 1, 2007 g eneral d escription the ics843031-01 is an 10gb ethernet clock generator and a member of the hiperclocks tm family of high performance devices from idt. the ics843031-01 uses an 18pf parallel resonant crystal. the ics843031-01 has excellent <1ps phase jitter performance, over the 1.875mhz - 20mhz integration range. the ics843031-01 is packaged in a small 8-pin tssop, making it ideal for use in systems with limited board space. f eatures ? one differential 3.3v or 2.5v lvpecl output ? crystal oscillator interface designed for 25mhz, 18pf parallel resonant crystal ? output frequencies: 280mhz ? 340mhz ? vco range: 560mhz - 680mhz ? rms phase jitter @ 312.5mhz, using a 25mhz crystal (1.875mhz - 20mhz): 0.46ps (typical) ? full 3.3v or 2.5v operating supply ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ics ics843031-01 8-lead tssop 4.40mm x 3.0mm x 0.925mm package body g package top view v cca v ee xtal_out xtal_in 1 2 3 4 v cc q nq oe 8 7 6 5 b lock d iagram xtal_in xtal_out q nq c ommon c onfiguration t able p in a ssignment oe pullup stupni ycneuqerftuptuo )zhm( )zhm(ycneuqerflatsyr cm n noitacilpitlum n/meulav 5 25 22 5 25 .213 osc phase detector vco m = 25 (fixed) n = 2 (fixed)
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 2 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator t able 2. p in c haracteristics t able 1. p in d escriptions lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu c ni ecnaticapactupni 4f p r nwodllup rotsiserpulluptupni 1 5k rebmu ne ma ne py tn oitpircsed 1v acc rewo p. nipylppusgolana 2v ee rewo p. nipylppusevitagen 4,3 ,tuo_latx ni_latx tupni ,tupniehtsini_latx.ecafretnirotallicsolatsyrc .tuptuoehtsituo_latx 5e ot upn ip ullu p. slevelecafretnilttvl/somcvl.nipelbanetuptuo 7, 6q ,q nt uptu o. slevelecafretnilcepvl.stuptuokcolclaitnereffid 8v cc rewo p. nipylppusrewop :eton pullup .seulavlacipytrof,scitsiretcarahcnip,2elbatees.srotsisertupnilanretniotsrefer tupn is tuptuo e oq n/q 0z -ih 1d elbane t able 3. oe f unction t able
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 3 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o contin uous current 50ma surge current 100ma package thermal impedance, ja 101.7c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4a. p ower s upply dc c haracteristics , v cc = 3.3v5%, t a = 0c to 70c t able 4c. lvcmos/lvttl dc c haracteristics , v cc = 3.3v5% or 2.5v5%, t a = 0c to 70c t able 4b. p ower s upply dc c haracteristics , v cc = 2.5v5%, t a = 0c to 70c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v cc egatlovylppusrewop 531. 33 . 35 64. 3v v acc egatlovylppusgolan av cc 21.0 ?3 . 35 64. 3v i acc tnerrucylppusgolana 2 1a m i ee tnerrucylppusrewop 50 1a m lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v cc egatlovylppusrewop 573. 25 . 25 26. 2v v acc egatlovylppusgolan av cc 21.0 ?5 . 25 26. 2v i acc tnerrucylppusgolana 2 1a m i ee tnerrucylppusrewop 0 9a m lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v hi egatlovhgihtupni v cc v3.3 =2 v cc 3.0 +v v cc v5.2 =7 . 1v cc 3.0 +v v li egatlovwoltupni v cc v3.3 =3 .0 -8 . 0v v cc v5.2 =3 .0 -7 . 0v i hi tnerruchgihtupn iv cc v= ni v526.2rov564.3 =5 a i li tnerrucwoltupn iv cc v,v526.2rov564.3= ni v0 =0 51 -a
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 4 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator t able 5. c rystal c haracteristics t able 6a. ac c haracteristics , v cc = 3.3v5%, t a = 0c to 70c t able 6b. ac c haracteristics , v cc = 2.5v5%, t a = 0c to 70c t able 4d. lvpecl dc c haracteristics , v cc = 3.3v5% or 2.5v5%, t a = 0c to 70c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v ho 1eton;egatlovhgihtuptu ov cc 4.1 -v cc 9.0 -v v lo 1eton;egatlovwoltuptu ov cc 0.2 -v cc 7.1 -v v gniws gniwsegatlovtuptuokaep-ot-kae p6 . 00 . 1v 05htiwdetanimretstuptuo:1eton vot cc .v2- retemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu noitallicsofoedom latnemadnuf ycneuqerf 4.2 25 22 .7 2z hm )rse(ecnat siserseirestnelaviuqe 04 ecnaticapactnuhs 7f p levelevird 00 3w m lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu f tuo ycneuqerftuptuo 08 25 .21 30 4 3z hm t )?(tij ;)modnar(rettijesahpsmr 1eton :egnarnoitargetni@zhm5.213 zhm02-zhm578.1 64. 0s p t r t/ f emitllaf/esirtuptu o% 08ot%0 20 5 10 0 5s p cd oe lcycytudtuptuo 8 42 5% .noitcessihtgniwollofstolpesionesahpehtotreferesaelp:1eton lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu f tuo ycneuqerftuptuo 08 25 .21 30 4 3z hm t )?(tij ;)modnar(rettijesahpsmr 1eton :egnarnoitargetni@zhm5.213 zhm02-zhm578.1 84. 0s p t r t/ f emitllaf/esirtuptu o% 08ot%0 20 5 10 0 5s p cd oe lcycytudtuptuo 8 42 5% .noitcessihtgniwollofstolpesionesahpehtotreferesaelp:1eton
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 5 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator t ypical p hase n oise at 312.5mh z a t 3.3v 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 312.5mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.46ps o ffset f requency (h z ) 100 1k 10k 100k 1m 10m 100m 10gb ethernet filter ? phase noise result by adding 10gb ethernet filter to raw data ? raw phase noise data ? dbc hz n oise p ower
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 6 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator scope qx nqx lvpecl p arameter m easurement i nformation o utput d uty c ycle /p ulse w idth /p eriod rms p hase j itter 3.3v o utput l oad ac t est c ircuit t pw t period t pw t period odc = x 100% q nq 2.5v o utput l oad ac t est c ircuit phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power 2v -1.3v 0.165v o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v sw i n g scope qx nqx lvpecl 2v -0.5v 0.125v v ee v cc 2v v cca v cca 2v v cc
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 7 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator a pplication i nformation f igure 2. c rystal i npu t i nterface c rystal i nput i nterface the ics843031-01 has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 2 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. c1 33p x1 18pf parallel crystal c2 27p xtal_out xtal_in p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics843031-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc and v cca should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. f igure 1. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v or 2.5v .01 f v cc
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 8 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50 . r2 zo = 50 vdd ro zo = ro + rs r1 vdd xta l _ i n xta l _ o u t .1uf rs t ermination for 3.3v lvpecl o utput the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal dis- tortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board design- ers simulate to guarantee compatibility across all printed circuit and clock component process variations. v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 9 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator t ermination for 2.5v lvpecl o utput figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. f igure 5c. 2.5v lvpecl t ermination e xample f igure 5b. 2.5v lvpecl d river t ermination e xample f igure 5a. 2.5v lvpecl d river t ermination e xample r2 62.5 zo = 50 ohm r1 250 + - 2.5v 2,5v lvpecl driv er r4 62.5 r3 250 zo = 50 ohm 2.5v vcc=2.5v r1 50 r3 18 zo = 50 ohm zo = 50 ohm + - 2,5v lvpecl driv er vcc=2.5v 2.5v r2 50 2,5v lvpecl driv er vcc=2.5v r1 50 r2 50 2.5v zo = 50 ohm zo = 50 ohm + -
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 10 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843031-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843031-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 105ma = 363.8mw ? power (outputs) max = 30mw/loaded output pair total power _max (3.465v, with all outputs switching) = 363.8mw + 30mw = 393.8mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.394w * 90.5c/w = 105.6c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 7. t hermal r esistance ? ? ja for 8- pin tssop, f orced c onvection ? ? ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 11 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc _max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc _max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 12 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator r eliability i nformation t ransistor c ount the transistor count for ics843031-01 is: 2377 t able 8. ja vs . a ir f low t able for 8 l ead tssop ? ? ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 13 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator p ackage o utline - g s uffix for 8 l ead tssop t able 9. p ackage d imensions reference document: jedec publication 95, mo-153 lobmys sretemillim mumini mm umixam n8 a- -0 2.1 1 a5 0. 05 1.0 2 a0 8. 05 0.1 b9 1. 00 3.0 c9 0. 00 2.0 d0 9. 20 1.3 ec isab04.6 1 e0 3. 40 5.4 ec isab56.0 l5 4 . 05 7.0 0 8 aa a- -0 1.0
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 14 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments. t able 10. o rdering i nformation rebmunredro/tra pg nikra me gakca pg nigakcapgnippih se rutarepmet 10-ga130348sc i1 0a1 3p osstdael 8e bu tc 07otc0 t10-ga130348sc i1 0a1 3p osstdael 8l eer&epat005 2c 07otc0 fl10-ga130348sc il 10a 1p osst"eerf-dael"dael 8e bu tc 07otc0 tfl10-ga130348sc il 10a 1p osst"eerf-dael"dael 8l eer&epat005 2c 07otc0 .tnailpmocshoreradnanotiarugifnoceerf-bpehterarebmuntrapehtotxiffus"fl"nahtiwderedroeratahtstrap:eton
idt ? / ics ? 3.3v, 2.5v lvpecl clock generator 15 ics843031ag-01 rev. a august 1, 2007 ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator teehsyrotsihnoisiver ve re lba te ga pe gnahcfonoitpircse de tad a3 t2 . elbatnoitcnufeodedda 70/32/1 a0 1 t4 1g nikrameerfdaeldedda-elbatnoitamrofniredro 70/1/8
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, the idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ics843031-01 femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator

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